 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| a 400 msps 14-bit, 1.8v cmos direct digital synthesizer preliminary technical data AD9952 rev. prb 1/31/2003 information furnished by analog dev i ces is believ ed to be accurate and reliable. how e v e r, no responsibility is assumed by analog dev i ces for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherw i se under any patent or patent rights of analog dev i ces. trademarks and registered trademarks are the property of their respectiv e companies. one technol ogy way , p. o. box 9106, nor w ood, m a 02062-9106, u. s. a . tel : 781/ 329-4700 www.anal og.com fax: 781/326-8703 ? 2002 a n alog dev i ces, inc. a ll rights reserv e d. features 400 msps internal clock speed in teg r ated 14-b i t d/a co n v erter pro g r ammab l e p h ase/amp litu d e d i th erin g 3 2 - bit tuning word ph ase no ise < = 125 d b c/hz @ 1khz o ffset (da c o u t p u t) excellen t dy n a mic perfo rman ce 80d b sf dr @ 130mhz (+ /- 100khz offset) a o u t serial i/o control ultra-h i g h sp eed an alo g co mp arato r , < 1 p s rms jitter 1 . 8 v pow e r supply softw a r e a nd ha rdw a re c ontrolle d pow e r dow n 48-lead epa d-t q f p p ackag e support for 5 v input le v e ls on mos t digita l inputs pll refclk multiplier (4x to 20x) internal oscillator, can be driv en by a single cry s tal phase modulation capability multi-chip synchronization applications a g ile l.o. frequency sy nthesis progra mma ble cloc k ge ne ra tor t est an d measu remen t eq u i p m en t a c ous to-optic de v i c e driv e r functional block diagram da c da c i-set aou t aou t sys t em cl ock t i ming & c ont rol logic i/ o upd a te re fc l k syn c out com p arato r io port c ontrol regis t er s sync r eset m u x 4x - 20x cl ock multi p ler s yst em cl oc k ref c lk os c illa t o r / bu f f e r sy n c 0 4 m u x p h ase accu mu lato r co s(x) phase off set dd s c o re 19 z -1 z -1 dds clock os k pw rdwn 32 32 32 14 analo g in + _ c l ock out crystal out en a b l e 14 phas e a ccum u l a t o r r e s e t f r eq ue n c y t un i n g w ord
preliminary technical data AD9952 rev. prb 1/31/03 page 2 analog devices, inc. general description the AD9952 is a direct digital synthesizer (dds) featuring a 14-bit dac operating up to 400msps. the AD9952 uses advanced dds technology, coupled with an internal high-speed, high performance d/a converter to form a digitally- programmable, complete high-fre quency synthesizer capable of generating a frequency-agile anal og output sinusoidal waveform at up to 200 mhz. the AD9952 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word). the frequency tuning and control words are loaded into the AD9952 via a serial i/o port. the device includes an on- chip high speed comparator for applications requiring a square wave output. the AD9952 is specified to operate over the extended industrial temperature range of -40 to +85c. absolute maximum ratings 1 storage temperatu re ........................-65 c to +150 c vs ................................................................ ........................ +4 v operating temp. ................................-40 c to +85 c digita l input volt age ......................................... .. -0.7 v to +vs digital output current ....................................... 5 ma t ja .................................................................................. 38c/w * absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. contents functional block diagram 1 general description 2 AD9952 preliminary electrical specifications 4 AD9952 pinmap 7 pin name 8 i/o 8 output spectral plots error! bookmark not defined. theory of operation 10 component blocks 10 dds core 10 phase truncation 11 clock input 11 phase locked loop (pll) 12 dac output 12 comparator 13 serial io port 13 register maps and descriptions 13 AD9952 register map 14 default 14 control register bit descriptions 15 control function register #1 (cfr1) 15 control function register #1 (cfr2) 19 other register descriptions 20 preliminary technical data AD9952 am plitude scale factor (asf) 20 amplitude ramp rate (arr) 20 frequency tuning word 0 (ftw0) 21 phase offset word (pow) 21 mode of operation 21 single tone mode 21 continuous and ?clear and release? phase accum u lator clear functions 21 continuous clear bit 21 clear and release function 21 program m i ng AD9952 features 22 phase offset control 22 phase/am plitude ditheringd 22 shaped on-off keying 23 auto shaped on-off keying m ode operation: 24 osk ramp rate timer 24 external shaped on-off keying m ode operation: 25 synchronization; register updates (i/o update) 25 functionality of the syncclk and i/o update 25 figure d- i/o synchroni zation block diagram 26 figure e - i/o synchroni zation tim i ng diagram 26 synchronizing multiple AD9952s error! bookmark not defined. using a single crystal to dr ive multiple AD9952 clock inputs error! bookmark not defined. serial port operation 28 instruction byte 29 serial interface port pin description 30 msb/lsb transqfers 30 example operation 31 notes on serial port operation 31 power down functions of the AD9952 31 AD9952 application suggestions 33 equivalent i/o circuits error! bookmark not defined. evaluation board layout error! bookmark not defined. evaluation board schem a tic error! bookmark not defined. evaluation board bom error! bookmark not defined. package outline dimensions error! bookmark not defined. rev. prb 1/31/03 page 3 a n alog d e vices , inc. preliminary technical data AD9952 AD9952 preliminary electrical specifications (unless otherwise noted: (v s =+1.8 v 5% , r set =1.96 k ? , external reference clock frequency = 20 mhz with refclk multiplier ena b led a t 2 0 ) param e t e r t e m p t e s t l e v e l a d 9 9 5 2 m i n typ m a x units ref clock input characteristics frequency range refclk multiplier disabled full vi 1 400 mhz refclk multiplier enabled at 4x full vi 20 100 mhz refclk multiplier enabled at 20x full vi 4 20 mhz input capacitance +25c v 3 pf input impedance +25c v 100 m ? duty cy cle +25c v 50 % duty cy cle with refclk multiplier enabled +25c v 35 65 % dac output characteristics r e s o l u t i o n 1 4 b i t s full scale output current +25c 5 10 15 ma gain error +25c i -10 +10 %fs output offset +25c i 0.6 a differential nonlinearity +25c v 1 lsb integral nonlinearity +25c v 2 lsb output capacitance +25c v 5 pf res i dual p h as e nois e @ 1 khz offs et, 40 m h z a out refclk multiplier enabled @ 20 + 2 5 c v - 8 9 d b c / h z refclk multiplier enabled @ 4 + 2 5 c v - 1 0 5 d b c / h z refclk multiplier disabled +25c v -116 dbc/hz voltage compliance range +25c i avdd- 0.375 a v d d + 0.25v v wideband sfdr: 1 ? 20 mhz analog out +25c v dbc 20 ? 40 mhz analog out +25c v dbc 40 ? 60 mhz analog out +25c v dbc 60 ? 80 mhz analog out +25c v dbc 80 ? 100 mhz analog out +25c v dbc 100 ? 120 mhz analog out +25c v dbc 120 ? 140 mhz analog out +25c v dbc 140 ? 160 mhz analog out +25c v dbc narrow band sfdr 10 mhz analog out (1 mhz) +25c v dbc 10 mhz analog out (250 khz) +25c v dbc 10 mhz analog out ( 50 khz) +25c v dbc 10 mhz analog out ( 10 khz) +25c v dbc 65 mhz analog out ( 1 mhz) +25c v dbc 65 mhz analog out ( 250 khz) +25c v dbc 65 mhz analog out ( 50 khz) +25c v dbc 65 mhz analog out ( 10 khz) +25c v dbc 80 mhz analog out ( 1 mhz) +25c v dbc 80 mhz analog out ( 250 khz) +25c v dbc 80 mhz analog out ( 50 khz) +25c v dbc 80 mhz analog out ( 10 khz) +25c v dbc 100 mhz analog out ( 1 mhz) +25c v dbc 100 mhz analog out ( 250 khz) +25c v dbc 100 mhz analog out ( 50 khz) +25c v dbc 100 mhz analog out ( 10 khz) +25c v dbc 120 mhz analog out ( 1 mhz) +25c v dbc 120 mhz analog out ( 250 khz) +25c v dbc 120 mhz analog out ( 50 khz) +25c v dbc 120 mhz analog out ( 10 khz) +25c v dbc 140 mhz analog out ( 1 mhz) +25c v dbc 140 mhz analog out ( 250 khz) +25c v dbc 140 mhz analog out ( 50 khz) +25c v dbc 140 mhz analog out ( 10 khz) +25c v dbc 160 mhz analog out ( 1 mhz) +25c v dbc rev. prb 1/31/03 page 4 a n alog d e vices , inc. preliminary technical data AD9952 rev. prb 1/31/03 page 5 analog devices, inc. 160 mhz analog out ( 250 khz) +25c v dbc parameter temp test min typ max units level 160 mhz analog out ( 50 khz) +25c v dbc 160mhz analog out ( 10 khz) +25c v dbc comparator input characteristics input capacitance +25c v 3 pf input resistance +25c iv 500 k : input current +25c i r 12 p a hysteresis +25c iv 30 45 mv comparator output characteristics logic ?1? voltage, high z load full vi +1.6 v logic ?0? voltage, high z load full vi +0.4 v propagation delay +25c iv 3 ns output duty cycle error 3 +25c iv 5 % rise/fall time, 5pf load +25c iv 1 ns toggle rate, high z load +25c iv mhz output jitter 4 +25c iv 1 ps rms comparator narrowband sfdr 2 10mhz (1mhz) 10mhz (250khz) 10mhz (50khz) 10mhz (10khz) 70mhz (1mhz) 70mhz (250khz) 70mhz (50khz) 70mhz (10khz) 110mhz (1mhz) 110mhz (250khz) 110mhz (50khz) 110mhz (10khz) 140mhz (1mhz) 140mhz (250khz) 140mhz (50khz) 140mhz (10khz) 160mhz (1mhz) 160mhz (250khz) 160mhz (50khz) 160mhz (10khz) +25c +25c +25c +25c +25c +25c +25c +25c +25c +25c +25c +25c +25c +25c +25c +25c +25c +25c +25c +25c v v v v v v v v v v v v v v v v v v v v 80 85 90 95 80 85 90 95 80 85 90 95 80 85 90 95 80 85 90 95 dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc clock generator output jitter 3 5 mhz a out 10 mhz a out 40 mhz a out 80 mhz a out 120 mhz a out 140 mhz a out 160 mhz a out +25c +25c +25c +25c +25c +25c +25c v v v v v v v 20 20 20 20 20 20 20 ps rms ps rms ps rms ps rms ps rms ps rms ps rms timing characteristics serial control bus maximum frequency minimum clock pulse width low (t pwl ) minimum clock pulse width high (t pwh ) maximum clock rise/fall time minimum data setup time (t ds ) minimum data hold time (t dh ) maximum data valid time (t dv ) wake-up time 2 minimum reset pulsewidth high (t rh ) full full full full full full full full full full iv iv iv iv iv iv iv iv iv iv 7 7 10 0 25 5 5 1 25 mhz ns ns ns ns ns ns ms sysclk cycles 5 cmos logic inputs logic ?1? voltage @ dvdd = 1.8v logic ?0? voltage @ dvdd = 1.8v logic ?1? voltage @ dvdd = 3.3v logic ?0? voltage @ dvdd = 3.3v logic ?1? current logic ?0? current input capacitance +25c +25c +25c +25c +25c +25c +25c i i i i v 1.25 2.2 3 0.6 0.8 12 12 v v v v p a p a pf cmos logic outputs (1ma load) dvdd=1.8v logic ?1? voltage logic ?0? voltage +25c +25c i i 1.35 0.4 v v preliminary technical data AD9952 p a r a m e t e r t e m p tes t min typ m a x un its l e v e l power supply +vs cu rren t full oper ating conditions 400 m h z clock 120 m h z clock power - d own m ode full-sleep mode +25 c +25 c +25 c +25 c +25 c +25 c i i i i i i 30 tbd tbd tbd tbd tbd ma ma ma ma ma ma notes 1 absolute m a xim u m ratings are lim iting values to be applied i ndividually, and be yond which the serviceability of the circuit m a y be im paired. functional operability under any of these conditions is not necessarily im plied. exposure of absolute m a xim u m ratin g co n d itio n s fo r ex ten d e d p e rio d s o f tim e affect d e v i ce reliab ility. 2 com p arator input originates from dds sec tion via external 7-pole elliptic lpf. si ngle-ended input, .5v p-p. com p arator out put t e rm i n at ed i n 50 ohm s . 3 rep r esen ts co m p arato r?s in h e ren t cycle-to -cycle j itter co n t rib u tio n . 4 w a ke-up ti m e refers t o recovery from anal og power down m ode s (see power down m odes of operat i on). the l ongest t i m e req u i red is fo r th e referen ce clo c k mu ltip lier pll to lo ck u p (if it is b e in g u s ed ). th e w a k e -up tim e assu m e s th at th ere is n o capacitor on dac_bp, and that the recom m e nded pll loop filter values are used. 5 sysclk refers to the actual clock freque ncy used on-chip by the AD9952. if the reference clock multiplier is used to m u ltip ly th e ex tern al referen ce freq u e n c y, th en th e sysclk freq u e n c y is th e ex tern al freq u e n c y m u ltip lied b y th e referen ce clo c k mu ltip lier m u ltip licatio n facto r . if th e referen ce clo c k mu ltip lier is n o t u s ed , th en th e sysclk freq u e n c y is th e sam e as the external refclk frequency. speci fi cat i ons are subject t o change wi t hout not i ce. settlin g tim e fo r crystal p o w er o n p o w er u p . (3 -4 m s ). ex planation of test levels i ? 100% product i on test ed. ii ? 100% product i on test ed at +25 c and sam p le tested at specified tem p eratures. iii ? sam p le tested only . iv ? param e t e r i s guarant eed by desi gn and charact eri zat i on t e st i ng. v ? param e t e r i s a t y pi cal val u e onl y . vi ? devi ces are 100% product i on t e st ed at +25c and guara nt eed by desi gn and charact eri zat i on t e st i ng for i ndust r i a l operat i ng t e m p erat ure range. ordering guide model temperature range package description package option AD9952asv -40c t o +85c 48-l ead qfp epad sv-48 AD9952pc b + 2 5 c eval uat i o n b o a r d caution esd (electrostatic discharge) s ensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge w i thout detection. although the AD9952 f eatures proprietary esd protection circuitry , permanent damage may occur on devices subjected to high-energy electrostatic discharges. t herefore, proper esd prec autions are recommended to avoid performance degradation or loss of functionality . rev. prb 1/31/03 page 6 a n alog d e vices , inc. preliminary technical data AD9952 AD9952 pinmap avd d os c/ r e f c l k os cb / r e f c l kb ag n d a d 9952 pi nout 48 leads 35 34 33 32 31 30 29 27 26 25 23 22 21 20 18 17 16 15 14 12 11 10 13 47 46 45 44 43 42 41 40 39 48 11 36 38 37 28 24 19 9 8 7 6 5 4 3 2 1 d a c b p d a c _ r s e t s y n c c l k dv dd i/o u p d a te d g n d d g n d o s k s c l k _ c s res e t s d i o d v d d _ i o dgnd s d o i o s y n c lo o p _f i l t e r dgnd dv dd d g n d pw r d w n c t l a g n d a v d d a v d d a g n d i o u t b i o u t a g n d a v d d c l km odes e l e ct cr y s t a l ou t com p _ i n com p _ i nb com p _ o ut avd d ag n d ag n d s y n c i n a g n d a v d d ag n d avd d avd d avd d figure 1 AD9952 pinmap rev. pra 1/31/03 page 7 a n alog d e vices , inc. preliminary technical data AD9952 hardw a re pin descriptions pin # pin name i/o description 1 i/o update i the rising edge transfers the contents of the internal buffer m e m o ry to the io registers. 2,34 dvdd i digital power supply pins. 3,33, 42, 47, 48 dgnd i digital power ground pins. 4,6, 13,16, 18,19, 25,27, 29 avdd i analog power supply pins. 5,7, 14,15, 17,22, 26,32 agnd i analog power ground pins. 8 oscb/refclkb i com p lem e ntary reference clock/oscillator input (400mhz m a x.). note: w h en the refclk port is operated in single-ended m ode, then refclkb should be decoupled to avdd with a 0.1 f capacitor. 9 osc/refclk i reference clock/oscillator input (400 mhz m a x.). see clock input section of datasheet for details on the refclk/oscillator operation. 10 crystal out o output of the oscillator section. 11 clkmodeselect i control pin for the oscillator section. w h en high, the oscillator section is enabled. w h en low, the oscillator section is bypassed. 12 loop_filter i this pin provides the connection for the external zero com p ensation network of the refclk multiplier?s pll loop filter. the network consists of a 1k ohm resistor in series with a 0.1 f capacitor tied to avdd. 20 ioutb o com p lem e ntary dac output. 2 1 i o u t o d a c o u t p u t . 23 dacbp i dac ?biasline? decoupling pin. 2 4 d a c _ r s e t i a resistor (3.85k ? nom inal) connected from agnd to dac_rset establishes the ref e rence current f o r the dac. 2 8 c o m p _ o u t o com p arator o u t p u t 3 0 c o m p _ i n i com p a r a t o r i n p u t 31 comp_inb i com p arator com p lem e ntary input 35 pwrdwnctl i input pin used as an external power down control. see the external power down control section of this docum ent for details. rev. pra 1/31/03 page 8 a n alog d e vices , inc. preliminary technical data AD9952 36 reset i active high hardware reset pin. assertion of the reset pin forces the AD9952 to the initial state, as described in the io port register m a p. 3 7 i o s y n c i asynchronous active high reset of the serial port controller. when high, the current io operation is im m e diately term inated enabling a new io operation to commence once iosync is returned low 3 8 s d o o when operating the i/o port as a 3-wire serial port this pin serves as the serial data output. when operated as a 2-wire serial port this pin is the unused and can be left unconnected. 3 9 c s - b a r i this pin functions as an active low chip select that allows multiple devices to share the io bus. 4 0 s c l k i this pin functions as the serial data clock for io operations 4 1 s d i o i / o when operating the i/o port as a 3-wire serial port this pin serves as the serial data input , only. when operated as a 2-wire serial port this pin is the bi- directional serial data pin. 43 dvdd_i/o i digital power supply (for io cells only, 3.3v optional) 4 4 s y n c _ i n i input signal used to synchronize multiple AD9952s. this input is connected to the sync_clk output of a different AD9952. 4 5 s y n c _ c l k o clock output pin, which serv es as a synchronizer for external hardware. table 1 hardware pin descriptions rev. pra 1/31/03 page 9 a n alog d e vices , inc. preliminary technical data AD9952 rev. pra 1/31/03 page 10 a n alog d evices , inc. theory of operation component blocks dds core the output frequency (f o ) of the dds is a function of the frequency of system clock ( sysclk), the value of the frequency tuning word (ftw ), and the capacity of the accumulator (2 32 , in this case). the exact relationship is given below with f s defined as the frequency of sysclk. f o = (ftw)(f s ) / 2 32 { 0 d ftw d 2 31 f o = f s* ( 1 ? ( ftw / 2 32 ) ) { 2 31 < ftw < 2 32 -1 the AD9952 frequency tuning word(s) are unsi gned numbers, where 80000000( hex) represents the highest output frequency possible, commonly re ferred to as the nyquist frequency. values ranging from than 80000001(hex) to ffffffff (hex) w ill be expressed as aliased frequencies less than nyquist. an example using a 3-bit phase ac cumulator will illustrate this principle. for a tuning word of 001, the phase accumulator output (p ao) increments from all zeros to all ones and repeats when the accumulator overfl ows after clock cycle number 8. for the tuning word of 111, the phase accumulator output (pao) decrements fro m all ones to all zeros and repeats when the accumulator overflows after clock cycle number 8. while the phase accumulator outputs are ?reversed? with respect to clock cycles, the outputs provide identical inputs to the phase to amplitude converter, which means the dds output frequencies are identical. mathematically, for a 3-bit accumulator, the following equations apply: f o = f s* (ftw / 2 3 ) { 0 d ftw d 2 2 f o = f s* ( 1 ? ( ftw / 2 3 ) ) { 2 2 < ftw < 2 3 -1 for the 001 frequency tuning word: fout = fs * 1/2 3 = 1/8*fs and for the 111 frequency tuning word: fout = fs * (1 ? 7/8) = 1/8*fs the value at the output of the phase accumulator is translated to an amplitude value via the cos(x) functional block and routed to the dac. preliminary technical data AD9952 rev. pra 1/31/03 page 11 a n alog d evices , inc. in certain applications it is desirable to force the output signal to zero phase. simply setting the ftw to 0 does not accomplish this. it only results in the dds core holding its current phase value. thus, a control bit is required to for ce the phase accumulator output to zero. at power up the clear phase accumulator bit is set to logic one but the buffe r memory for this bit is cleared (logic zero). therefore, upon power up, the phase accumulator will remain clear until the first i/o update is issued. phase truncation the 32-bit phase values generated by the phase accu mulator are truncated to 19 bits prior to the cos(x) block. that is, the 19 most significant bits of phase are retained for subsequent processing. this is typical of standard dds architecture and is a trade off between hardware complexity and spurious performance. it can be shown that 19-bit phase resolution is sufficient to yield 14-bit amplitude resolution with an error of less than ? lsb. the decision to truncate at 19 bits of phase guarantees the phase error of the cos(x) block to be less than the phase error associated with the amplitude resolution of the 14-bit dac. clock input the AD9952 supports various clock methodologies. support for differential or single-ended input clocks, enabling of an on-chip oscillator and/or phase-locked loop (pll) multiplier are all controlled via user programmable bits. the ad 9952 may be configured in one of six operating modes to generate the system clock. the mode s are configured using the clkmodeselect pin, cfr2<0>, and cfr2<7:3>. connecting the external pin clkmodeselect to logic high enables the on-chip crystal oscillator circuit. with th e on-chip oscillator enabled, users of the AD9952 connect an external crystal to the refclk and refclkb inputs to produce a low frequency reference clock in the range of 20-30mhz. the signa l generated by the oscillator is buffered before it is delivered to the rest of th e chip. this buffered signal is available via the crystal out pin. bit cfr2<0> can be used to enable or disable the buffer, turning on or off the system clock. the oscillator itself is not powered down in order to avoid long start-up times associated with turning on a crystal oscillator. writing bit cfr2<1> to l ogic high enables the crystal oscillator output buffer. logic low at cfr2<1> disables the oscillator output buffer. connecting clkmodeselect to logic low disables the on-chip oscillator and the oscillator output buffer. with the oscillator disabl ed an external oscillator must provide the refclk and/or refclkb signals. for differential operation these pins are driven with complementary signals. for single-ended operation a 0.1uf capacitor should be connected between the unused pin and the positive power supply. with the capacitor in place the clock input pin bias voltage is 1.35v. in addition, the pll may be used to multiply the reference frequency by an integer value in the range of the 4 to 20. the modes of operation are summarized in the ta ble below. please note the pll multiplier is controlled via the cfr2<7:3> bits, i ndependently of the cfr2<0> bit. preliminary technical data AD9952 rev. pra 1/31/03 page 12 a n alog d evices , inc. clkmodeselect cfr2<0> cfr2<7:3> system clock frequency range (mhz) high low 3 < m < 21 f clk = f osc x m 80 < f clk < 400 high low m < 4 or m > 20 f clk = f osc 20 < f clk < 30 high high x f clk = 0 f clk = 0 low x 3 < m < 21 f clk = f ref x m 80 < f clk < 400 low x m < 4 or m > 20 f clk = f ref 5 < f clk < 400 table 2 clock input modes of operation phase locked loop (pll) the pll is required to facilitate multiplication of the refclk frequency. control of the pll is accomplished by programming the 5-bit refclk multiplier portion of control function register #2, bits <7:3>. when programmed for values ranging from 04h ? 14h (4-20 decimal), the pll multiplies the refclk input frequency by the co rresponding decimal value. th e maximum output frequency of the pll is restricted to 400mhz, however. whenev er the pll value is changed, the user should be aware that time must be allocated to a llow the pll to lock (approximately 1ms). the pll is bypassed by programming a value outsi de the range of 4-20 (decimal). when bypassed, the pll is shut down to conserve power. dac output the AD9952 incorporates an integrated 14-bit current output dac. two complementary outputs provide a combined full-scale output current (i out ). differential outputs reduce the amount of common-mode noise that might be present at the dac output, offering the advantage of an increased signal-to-noise ratio. the full-scale current is controlled by means of an external resistor (r set ) connected between the dac_rset pin a nd the dac ground (agnd_dac). the full-scale current is proportional to the resistor value as follows: r set = 39.19/i out the maximum full-scale output current of the co mbined dac outputs is preliminary technical data AD9952 rev. pra 1/31/03 page 13 a n alog d evices , inc. comparator many applications require a square wave signal ra ther than a sine wave. for example, in most clocking applications a high slew rate helps to reduce phase noise and jitter. to support these applications, the AD9952 includes an on-chip compar ator. the comparator has a bandwidth greater than 200mhz and a common mode i nput range of 1.3v to 1.8v. by setting the comparator power- down bit, cfr1<6>, the comparator can be turned off to save on power consumption. serial io port the AD9952 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry standard micro-controlle rs and microprocessors. the serial i/o port is compatible with most synchronous transfer fo rmats, including both the motorola 6905/11 spi and intel 8051 ssr protocols. the interface allows read/write access to all regist ers that configure the AD9952. msb first or lsb first transfer formats are supported. in add ition, the AD9952?s serial interface port can be configured as a single pin i/o (sdio), which allows a two-wire interface or two unidirectional pins for in/out (sdio/sdo), which enables a three wire interface. two optional pins (iosync and csb) enable greater flexibility for system design-in of the AD9952. register maps and descriptions the register maps are listed in the following tables. the serial address numbers associated with each of the registers are shown in hexad ecimal format. angle brackets <> are used to reference specific bits or ranges of bits. for ex ample, <3> designates bit 3 while <7:3> designates the range of bits from 7 down to 3, inclusive. preliminary technical data AD9952 rev. pra 1/31/03 page 14 a n alog d evices , inc. AD9952 register map register name (serial address) bit range (internal address) (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value <7:0> (00h) digital power down comp power down dac power down clock input power dwn external power down mode open sync clk out disable open 00h <15:8> (01h) open open autoclr phase accum enable sine output open clear phase accum. sdio input only lsb first 00h <23:16> (02h) automatic sync enable software manual sync open amplitude dither enable phase dither en<3> phase dither en<2> phase dither en<1> phase dither en<0> 00h control function register #1 (cfr1 ) (00h) <31:24> (03h) open load arr @fud output shaped keying enable auto output shaped keying 00h <7:0> (04h) refclk multiplier 00h or 01h or 02h or 03h: bypass multiplier 04h ?14h: 4x ? 20x multiplication vco gain charge pump control <1:0> 00h <15:8> (05h) open high speed sync enable hardware manual sync enable crystal out pin active dac prime data disable 00h control function register #2 (cfr2) (01h) <23:16> (06h) open 00h <7:0> (07h) amplitude scale factor register <7:0> - amplitude scale factor (asf ) (02h) <15:8> (08h) auto ramp rate speed control <1:0> amplitude scale factor register <13:8> - amplitude ramp rate (arr) (03h) <7:0> (09h) amplitude ramp rate register <7:0> - <7:0> (0ah) frequency tuning word #0 <7:0> 00h <15:8> (0bh) frequency tuning word #0 <15:8> 00h <23:16> (0ch) frequency tuning word #0 <23:16> 00h frequency tuning word (ftw0) (04h) <31:24> (0dh) frequency tuning word #0 <31:24> 00h <7:0> (0eh) phase offset word #0 <7:0> 00h phase offset word (pow0 ) (05h) <15:8> (0fh) open<1:0> phase offset word #0 <13:8> 00h preliminary technical data AD9952 rev. pra 1/31/03 page 15 a n alog d evices , inc. control register bit descriptions control function register #1 (cfr1) the cfr1 is used to control the various func tions, features, and modes of the AD9952. the functionality of each bit is detailed below. cfr1<26>: amplitude ramp rate load control bit. when cfr1<26> = 0 (default) , the amplitude ramp rate timer is loaded only upon timeout (timer ==1) and is not loaded due to an i/o update input signal. when cfr1<26> = 1, the amplitude ramp rate timer is loaded upon timeout (timer ==1) or at the time of an i/o update input signal. cfr1<25>: shaped on-off keying enable bit. when cfr1<25> = 0 (default,) shaped on-off keying is bypassed. when cfr1<25> = 1, shaped on-off ke ying is enabled. when enabled, cfr1<24> controls the mode of operation for this function. cfr1<24>: auto shaped on-off keying enable bit (only valid when cfr1<25> is active high). when cfr1<24> = 0 (default). when cfr1<25> is active, a logic 0 on cfr1<24> enables the manual shaped on -off keying operation. see the shaped on-off keying section of this document for details. when cfr1<24> = 1, if cfr1<25> is ac tive, a logic 1 on cfr1<24> enables the auto shaped on-off keying operation. see the shaped on-off keying section of this document for details. cfr1<23>: automatic synchronization mode. when cfr1<23> = 0 (default), the automatic synchronization of multiple AD9952s feature is inactive. when cfr1<23> = 1, the automatic sync hronization feature is active. see the synchronizing multiple AD9952s section of this document for details. preliminary technical data AD9952 rev. pra 1/31/03 page 16 a n alog d evices , inc. cfr1<22>: software manual synchronization mode. when cfr1<22> = 0 (default), the manual synchronization of multiple AD9952s feature is inactive. when cfr1<22> = 1, the software cont rolled manual synchronization feature is executed. the sync_clk rising edge is advanced by one sysclk cycle and this bit is cleared. to advance the rising edge mu ltiple times, this bit needs to be set for each advance. see the synchronizing multiple AD9952s section of this document for details. . cfr1<20>: amplitude dither enable bit. when cfr1<20> = 0 (default) , amplitude dithering is disabled. when cfr1<20> = 1, amplitude dithering is enabled. cfr1<19>: phase bit <16> dither enable bit. when cfr1<19> = 0 (default) , phase dithering for truncated phase words, bit 16 of <31:13>, is disabled. when cfr1<19> = 1, phase dithering for truncated phase words, bit 16 of <31:13>, is enabled. cfr1<18>: phase bit <15> dither enable bit. when cfr1<18> = 0 (default) , phase dithering for truncated phase words, bit 15 of <31:13>, is disabled. when cfr1<18> = 1, phase dithering for truncated phase words, bit 15 of <31:13>, is enabled. cfr1<17>: phase bit <14> dither enable bit. when cfr1<17> = 0 (default) , phase dithering for truncated phase words, bit 14 of <31:13>, is disabled. when cfr1<17> = 1, phase dithering for truncated phase words, bit 14 of <31:13>, is enabled. preliminary technical data AD9952 rev. pra 1/31/03 page 17 a n alog d evices , inc. cfr1<16>: phase bit <13> dither enable bit. when cfr1<16> = 0 (default) , phase dithering for truncated phase words, bit 13 of <31:13>, is disabled. when cfr1<16> = 1, phase dithering for truncated phase words, bit 13 of <31:13>, is enabled. cfr1<13>: autoclear phase accumulator bit. when cfr1<13> = 0 (default) , a new frequency tuning word is applied to the inputs of the phase accumulator, but not loaded into th e accumulator. when cfr1<13> = 1, this bit automatically synchronously clears (loads zeros into) the phase accumulator for one cycle upon reception of the i/o update sequence indicator. cfr1<12>: sine/cosine select bit. when cfr1<12> = 0 (default) , the angle-to-amplitude conversion logic employs a cosine function. when cfr1<12> = 1, the angle-to-amp litude conversion logic employs a sine function. cfr1<10>: clear phase accumulator. when cfr1<10> = 0 (default) , the phase accumulator functions as normal. when cfr1<10> = 1, the phase accumula tor memory elements are asynchronously cleared. cfr1<9>: sdio input only. when cfr1<9> = 0 ( default ), the sdio pin has bi-directional operation (2-wire serial programming mode). when cfr1<9> = 1, the serial data i/o pin (sdio) is configured as an input only pin (3-wire serial programming mode). preliminary technical data AD9952 rev. pra 1/31/03 page 18 a n alog d evices , inc. cfr1<8>: lsb first. when cfr1<8> = 0 ( default ), msb first format is active. when cfr1<8> = 1, the serial interface a ccepts serial data in lsb first format. cfr1<7>: digital power down bit. when cfr1<7> = 0 ( default ), all digital functions and clocks are active. when cfr1<7> = 1, all non-io digital f unctionality is suspended and all heavily loaded clocks are stopped. this bit is inte nded to lower the digital power to nearly zero, without shutting down the pll cl ock multiplier function or the dac. cfr1<6>: comparator power down bit. when cfr1<6> = 0 ( default ), the comparator is enabled for operation. when cfr1<6> = 1, the comparator is disabled and is in its lowest power dissipation state. cfr1<5>: dac power down bit. when cfr1<5> = 0 ( default ), the dac is enabled for operation. when cfr1<5> = 1, the dac is disabled and is in its lowest power dissipation state. cfr1<4>: clock input power down bit. when cfr1<4> = 0 ( default ), the clock input circuitry is enabled for operation. when cfr1<4> = 1, the clock input circuitr y is disabled and the device is in its lowest power dissipation state. cfr1<3>: external power down mode. when cfr1<3> = 0 (default) the external power down mode selected is the ?fast recovery power down? mode. in this mode , when the pwrdwnctl input pin is high, the digital logic and the dac digital logic are powered down. the dac bias circuitry, comparator, pll, oscillator, a nd clock input circuitry is not powered down. when cfr1<3> = 1, the external power down mode selected is the ?full power down? mode. in this mode, when the pwrdwn ctl input pin is high, all functions are preliminary technical data AD9952 rev. pra 1/31/03 page 19 a n alog d evices , inc. powered down. this includes the dac and pll, which take a significant amount of time to power up. cfr1<1>: syncclk disable bit. when cfr1<1> = 0 (default) , the syncclk pin is active. when cfr1<1> = 1, the syncclk pin assumes a static logic 0 state (disabled). in this state the pin drive logic is shut dow n to keep noise generated by the digital circuitry at a minimum. however, the synchronization circuitry remains active (internally) to maintain normal device timing. cfr1<0>: not used. leave at 0. note: assertion of this bit may cause th e syncclk pin to momentarily stop generating a sync cloc k signal. the device will not be operational during the re- synchronization period. control function register #2 (cfr2) cfr2<15:12>: not used. cfr2<11>: high speed sync enable bit. when cfr2<11> = 0 (default) the high speed sync enhancement is off. when cfr2<11> = 1, the high speed sync enhancement is on. see the synchronizing multiple AD9952s section of this document for details. cfr2<10>: hardware manual sync enable bit. when cfr2<10> = 0 (default) the hardware manual sync function is off. when cfr2<11> = 1, the hardware manual s ync function is enabled. while this bit is set, a rising edge on the sync_in pi n will cause the device to advance the sync_clk rising edge by one refclk cy cle. unlike the software manual sync enable bit, this bit does not self-clear. once the hardware manual sync mode is enabled, it will stay enabled until this bit is cleared. see the synchronizing multiple AD9952s section of this document for details. preliminary technical data AD9952 rev. pra 1/31/03 page 20 a n alog d evices , inc. cfr2<9>: crystal out enable bit. when cfr2<9> = 0 (default) the crystal out pin is inactive. when cfr2<9> = 1, the crystal out pin is ac tive. when active, the crystal oscillator circuitry output drives the crystal out pin, which can be connected to other devices to produce a reference frequency. cfr2<8>: dac prime data disable bit. when cfr2<8> = 0 ( default ), the dac prime data is enabled for operation. when cfr2<8> = 1, the dac prime data is not generated and these outputs remain logic zeros. cfr2<7:3>: reference clock multiplier control bits. see the phase locked loop (pll) section of this document for details. cfr2<2>: vco gain control bit. this bit is us ed to control the gain setting on the vco. cfr<1:0>: charge pump gain control bits. these bits are used to control the gain setting on the charge pump. other register descriptions amplitude scale factor (asf) the asf register stores the 2-bit auto ramp rate speed value asf<15:14> and the 14-bit amplitude scale factor asf<13:0> used in the output shaped keying (osk) operation. in auto osk operation, that is cfr1<24> = 1, asf < 15:14> tells the osk block how many amplitude steps to take for each incremen t or decrement. asf<13:0> sets the maximum value achievable by the osk internal multiplier. in manual osk mode , that is cfr1<24>=0, asf<15:14> have no affect. asf <13:0> provide the out put scale factor directly. if the osk enable bit is cleared, cfr1<25>=0, this register has no affect on device operation. amplitude ramp rate (arr) the arr register stores the 8-bit amplitude ramp rate used in the auto osk mode, that is cfr1<25>=1, cfr<24>=1. this register programs the rate the amplitude scale factor counter increments or decrements. in the osk is set to manual mode, cfr1<25>=1 cfr<24>=0, or if osk enable is cleared cfr1<25>=0, this register has no affect on device operation. preliminary technical data AD9952 rev. pra 1/31/03 page 21 a n alog d e vices , inc. frequency tuning word 0 (ftw0) the frequency tuning word is a 32-bit register that controls the rate of accumulation in the phase accumulator of the dds core. phase offset word (pow) the phase offset word is a 14-bit register that st ores a phase offset value. this offset value is added to the output of the phase accumulator to o ffset the current phase of the output signal. the exact value of phase offset is given by the following form ula: ? ? ? ? ? ? = 360 * 2 14 pow mode of operation single tone mode the dds core uses a single tuning word. whatever value is stored in ftw0 is supplied to the phase accumulator. this value can only be cha nged statically, which is done by writing a new value to ftw0 and issuing an i/o update. phase adjustm e nt is possible through the phase offset register. c ont i nuous and ?c l e ar and rel e ase? phase accumul a t o r c l ear funct i ons the AD9952 allows for a program m a ble continuous zer oing of the phase accum u lator as well as a ?clear and release?, or automatic zeroing function. each feature is individually controlled via bits the cfr1. cfr1<13> is the autom a tic clear ph ase accum u lator bit. cfr1<10> continuously clears the phase accumulator. c ont i nuous c l ear bi t the continuous clear bits are sim p ly static contro l signals that, when active high, holds the phase accumulator at zero for the entire tim e the bit is active. when the bit goes low, inactive, the phase accumulator is allowed to operate. c l ear and rel e ase f unct i on the auto clear phase accum u la tor, when set, clears and releases the phase accum ulator upon receiving an i/o update. the automatic clearing f unction is repeated for every subsequent i/o update until the appropriate auto-clear control bit is cleared. preliminary technical data AD9952 rev. pra 1/31/03 page 22 a n alog d evices , inc. programming AD9952 features phase offset control a 14-bit phase-offset ( t ) may be added to the output of the phase accumulator by means of the control registers. this feature provides the user with two different methods of phase control. the first method is a static phase adjustment, where a fixed phase-offset is loaded into the appropriate phase-offset register a nd left unchanged. the result is th at the output signal is offset by a constant angle relative to the nominal signal. th is allows the user to phase align the dds output with some external signal, if necessary. the second method of phase control is where the user regularly updates the phase-offset register via the i/o port. by properly modifying the pha se-offset as a function of time, the user can implement a phase modulated output signal. ho wever, both the speed of the i/o port and the frequency of sysclk limit the rate at whic h phase modulation can be performed. phase/amplitude dithering the AD9952 dds core includes optional phase and/ or amplitude dithering controlled via the cfr1<20:16> bits. phase dithering is the randomization of the state of the least significant bits of each phase word. phase dithering reduces spurious signal strength caused by phase truncation by spreading the spurious energy over the entire spectrum. the downsid e to dithering is a rise in the noise floor. amplitude dithering is similar, except it a ffects the output signal routed to the dac. phase dithering is independently controlled on the four least significant bits of the phase word routed to the angle rotation function. that is, any or all of the phase word four least significant bits may be dithered or not dithered, controlled by th e user via the serial port. specifically, the cfr1<19> bit controls the phase dithering enab le function of the phase word <16> bit. the cfr1<18> bit controls the phase dithering enab le function of the phase word <15> bit. the cfr1<17> bit controls the phase dithering enab le function of the phase word <14> bit. the cfr1<16> bit controls the phase dithering enable function of the phase word <13> bit. this enable function is such that if the bit is high, dithering is enabled. if the bit is low, dithering is not enabled. amplitude dithering uses one control bit to enable or disable dithering. if the amplitude dither enable bit (cfr1<20>) is logic 0, no amplitude dithering is enabled and the data from the dds core is passed unchanged. when high, amplitude dithering is enabled. preliminary technical data AD9952 rev. pra 1/31/03 page 23 a n alog d e vices , inc. shaped on-off keying general description: the shaped on-off keying function of the AD9952 allows the user to control the ram p -up and ram p -down tim e of an ? on-off? em ission from the dac. this function is used in ?burst transm issions? of digital data to reduce the adverse spectral im pact of short, abrupt bursts of data. auto and manual shaped on-off keying m odes ar e supported. the auto m ode generates a linear scale factor at a rate determined by the am plitude ram p rate (arr) register controlled by an external pin (osk). manual mode allows the us er to directly control the output amplitude by writing the scale factor value into the amp litude scale factor (asf) register (asf). the shaped on-off keying function m a y be bypassed (disabled) by clearing the osk enable bit (cfr1<25>=0). the m odes are controlled by two bits located in th e m o st significant byte of the control function register (cfr). cfr1<25> is the shaped on-off ke ying enable bit. when cfr1<25> is set, the output scaling function is enable d; cfr1<25> bypasses the function. cfr1<24> is the internal shaped on-off keying active bit. wh en cfr1<24> is set, internal shaped on-off keying m ode is active; cfr1<24> cleared is ex ternal shaped on-off keying mode active. cfr1<24> is a ?don?t care? if the shaped on-off keyi ng enable bit (cfr1<25>) is cleared. the power up condition is shaped on-off keying disabled (cfr1<25> = 0). figure c below shows the block diagram of the osk circuitry. co s(x ) dd s co re to d a c osk en able cfr<25> 0 1 amplit u de scale f a ct or r e gist er (asf ) 0 1 0 0 1 out hold up /dn osk pi n a m plitud e ramp rate registe r (arr ) loa d data en load os k timer cfr1<26> sy nc clo c k clock inc/dec ena b le ra mp rat e time r aut o scale factor ge nerator auto o s k ena b le cfr<24> preliminary technical data AD9952 rev. pra 1/31/03 page 24 analog devices, inc. figure c. on-off shaped keying, block diagram auto shaped on-off keying mode operation: the auto shaped on-off keying mode is active when cfr1<25> and cfr1<24> are set. when auto shaped on-off keying mode is enabled, a si ngle scale factor is internally generated and applied to the multiplier input for scaling the output of the dds core block (see figure 9 above). the scale factor is the output of a 14-bit counter which increments/decrements at a rate determined by the contents of the 8-bit output ramp rate regist er. the scale factor increases if the osk pin is high, decreases if the pin is low. the scale factor is an unsigned value such that all zeros multiplies the dds core output by 0 (decimal) and 3fffh multiplies the dds core output by 16383 decimal. for those users who use the full amplitude (14-bits ) but need fast ramp rates, the internally generated scale factor step size is controlled vi a the asf<15:14> bits. the table below describes the increment/decrement step size of the internally generated scale factor per the asf<15:14> bits. asf<15:14> (binary) increment/decrement size 00 1 01 2 10 4 11 8 table 5 auto-scale factor internal step size a special feature of this mode is that the maximum output amplitude allowed is limited by the contents of the amplitude scale factor register. th is allows the user to ramp to a value less than full scale. osk ramp rate timer the osk ramp rate timer is a loadable down count er, which generates the clock signal to the 14-bit counter that generates the internal scale factor. th e ramp rate timer is load ed with the value of the asfr every time the counter reaches 1 (decimal). this load and count down operation continues for as long as the timer is enabled unless the timer is forced to load before reaching a count of 1. if the load osk timer bit (cfr1<26>) is set, th e ramp rate timer is loaded upon an i/o update or upon reaching a value of 1. the ramp timer can be loaded before reaching a count of 1 by three methods. method one is by changing the osk input pin. when the osk input pin changes state the asfr value is loaded into the ramp rate timer, which then proceeds to count down as normal. preliminary technical data AD9952 rev. pra 1/31/03 page 25 analog devices, inc. the second method in which the sweep ramp rate tim er can be loaded before reaching a count of 1 is if the load osk timer bit (cfr1<26>) bit is set and an i/o update is issued. the last method in which the sweep ramp rate timer can be loaded before reaching a count of 1 is when going from the inactive auto shaped on-off keying mode to the active auto shaped on-off keying mode. that is, when the sweep enable bit is being set. external shaped on-off keying mode operation: the external shaped on-off keying mode is enabled by writing cfr1<25> to a logic 1 and writing cfr1<24> to a logic 0. when configured for external shaped on -off keying, the content of the asfr becomes the scale factor for the da ta path. the scale factors are synchronized to sync_clk via the i/o update functionality. synchronization; register updates (i/o update) functionality of the syncclk and i/o update data into the AD9952 is synchronous to the syncclk pin. that is, the i/o update pin is sampled on the rising edge of the s yncclk clock provided by the AD9952. as shown in the figure d, sysclk is fed to a divide-by-4 frequency divi der to produce sync_clk sync_clk is also provided to the user on the syncclk pin. this enables synchronization of external hardware with the AD9952?s internal dds clock. this is accomplished by forcing any external hardware to obtain its timing from syncclk. exte rnal hardware that is timed using the syncclk signal can then be used to provide the i/ o update signal to the AD9952. the i/o update signal coupled with syncclk is used to transfer in ternal buffer register contents into the control registers of the device. the combination of th e syncclk and i/o update pins provides the user with constant latency relative to sysclk and al so ensures phase continuity of the analog output signal when a new tuning word or phase offset va lue is asserted. figure e demonstrates an i/o update timing cycle and synchronization. notes to synchronization logic: 1) the i/o update signal is edge detected to generate a single rising edge clock signal that drives the register bank flops. the i/o update signal has no constraints on duty cycle. 2) the minimum low time on i/o upda te is one sync_clk clock cycle. the i/o update pin is setup and held around the rising edge of sync_clk and has zero hold time and 10ns setup time. preliminary technical data AD9952 rev. pra 1/31/03 page 26 a n alog d e vices , inc. 0 1 0 sy nc clk disa ble d q d q d q os k p r ofile<1:0> i/o upda t e e dge detectio n lo gic synccl k gating register me m o ry i/o buff er latches sc lk sdi cs to core logic sy sclk 4 figure d- i/o synchroniz ation block diagram data [1] data[ 1 ] d a t a(2) data (2) d ata(3) dat a ( 3 ) ab sy sc l k sy nclk i/o update data in registe r s data in i/o b u ffers t he device regist ers an i / o u pdate at point a. t h e data is t r an f e rred f r o m the asynch ronously load ed i / o buf fers at p o int b. figure e - i/o synchroniz ation timing diagram preliminary technical data AD9952 rev. pra 1/31/03 page 27 analog devices, inc. synchronizing multiple AD9952s the AD9952 product allows easy sync hronization of multiple AD9952s. there are three modes of synchronization available to the user: an automatic synchronization mode; a software controlled manual synchronization mode; and a hardware controlled manual synchronization mode. in all cases, when a user wants to synchronize two or mo re devices, the following considerations must be observed. first, all units must share a common clock source. trace lengths and path impedance of the clock tree must be designed to keep the phase delay of the different clock branches as closely matched as possible. second, the i/o update signa l?s rising edge must be provided synchronously to all devices in the system. finally, regardless of the internal synchronization method used, the dvdd_i/o supply should be set to 3.3v for all devices that are to be synchronized. avdd and dvdd should be left at 1.8v. in automatic synchronization mode, one device is chosen as a master, the other device(s) will be slaved to this master. when configured in this mode, all the slaves will automatically synchronize their internal clocks to the sync_clk output signal of the master device. to enter automatic synchronization mode, set the slav e device?s automatic synchronization bit (cfr1<23>=1). connect the sync_in input(s) to the master sync_clk output. the slave device will continuously update the pha se relationship of its sync_clk until it is in phase with the sync_in input, which is the sync_clk of the master device. when attempting to synchronize devices running at sysclk speeds beyond 250msps, th e high-speed sync enhancement enable bit should be set (cfr2<11>=1). in software manual synchronization mode, the user forces the device to advance the sync_clk rising edge one sysclk cycle (1/4 sync_clk period). to activate the manual synchronization mode, set the slave device?s so ftware manual synchronization bit (cfr1<22> =1). the bit (cfr1<22>) will be immediately cleared. to advance the rising edge of the sync_clk multiple times, this bit will n eed to be set multiple times. in hardware manual synchronization mode, the s ync_in input pin is configured such that it will now advance the rising edge of the sync_clk signal each time the device detects a rising edge on the sync_in pin. to put the device into hardware manual synchronization mode, set the hardware manual synchronization bit (cfr2<10>=1 ). unlike the software manual synchronization bit, this bit does not self-clear. once the hard ware manual synchronization mode is enabled, all rising edges detected on the sync_in input will caus e the device to advance the rising edge of the sync_clk by one sysclk cycle until this enable bit is cleared (cfr2<10=0). using a single crystal to dri ve multiple AD9952 clock inputs the AD9952 crystal oscillator output signal is availa ble on the crystalout pin, enabling one crystal to drive multiple AD9952s. in order to drive multiple AD9952s with one crystal, the crystalout pin of the AD9952 using the external crystal shoul d be connected to the refclk input of the other AD9952. the crystalout pin is static until the cfr2<1> bit is set, enabling the output. the drive strength of the crystalout pin is typically very low, so this signal should be buffered prior to using it to drive any loads. preliminary technical data AD9952 rev. pra 1/31/03 page 28 analog devices, inc. serial port operation with the AD9952, the instruction by te specifies read/write operation and register address. serial operations on the AD9952 occur only at the register level, not the byte level. for the AD9952, the serial port controller recognizes the instruction by te register address and automatically generates the proper register byte address. in addition, the cont roller expects that all bytes of that register will be accessed. it is a requirement that all bytes of a register be accessed during serial i/o operations, with one exception. the syncio function can be used to abort an io operation thereby allowing less than all bytes to be accessed. there are two phases to a communication cycle with the AD9952. phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9952, coincident with the first eight sclk rising edges. the instruction byte provides the AD9952 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data tr ansfer is read or write and the serial address of the register being accessed. [note ? the serial address of the register being accessed is not the same address as the bytes to be written. see th e example operation section below for details]. the first eight sclk rising edges of each communi cation cycle are used to write the instruction byte into the AD9952. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between th e AD9952 and the system controller. the number of bytes transferred during phase 2 of the communica tion cycle is a function of the register being accessed. for example, when accessing the control f unction register 2, which is three bytes wide, phase 2 requires that three bytes be transferred. if accessing the frequency tuning word, which is four bytes wide, phase 2 requires th at four bytes be transferred. af ter transferring all data bytes per the instruction, the communi cation cycle is completed. at the completion of any communication cycle, th e AD9952 serial port controller expects the next 8 rising sclk edges to be the instruction byte of the next communication cycle.all data input to the AD9952 is registered on the rising edge of sclk. all data is driven out of the AD9952 on the falling edge of sclk. figures 34 - 37 are useful in understanding the general operation of the AD9952 serial port. preliminary technical data AD9952 rev. pra 1/31/03 page 29 a n alog d e vices , inc. instruction by te the instruction byte contains the following in form ation as shown in the table below: instruction byte information m s b d 6 d 5 d 4 d 3 d 2 d 1 l s b r / w b x x a 4 a 3 a 2 a 1 a 0 table 6 instruction byte r/-wb?bit 7 of the instruction byte determines wh ether a read or write data transfer will occur after the instruction byte write. logic high indicate s read operation. logic zero indicates a write operation. preliminary technical data AD9952 rev. pra 1/31/03 page 30 analog devices, inc. x, x?bits 6 and 5 of the instruction byte are don?t care. a4, a3, a2, a1, a0?bits 4, 3, 2, 1, 0 of the in struction byte determine which register is accessed during the data transfer portion of the communications cycle. serial interface port pin description sclk ? serial clock. the serial clock pin is us ed to synchronize data to and from the AD9952 and to run the internal state machines. sclk maximum frequency is 25 mhz. csb ? chip select bar. active low input that allo ws more than one device on the same serial communications line. the sdo and sdio pins will go to a high impedance state when this input is high. if driven high during any communications cycle, that cy cle is suspended until cs is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdio ? serial data i/o. data is always written into the AD9952 on this pin. however, this pin can be used as a bi-directional data line. bit 7 of register address 0h contro ls the configuration of this pin. the default is logic zero, which c onfigures the sdio pin as bi-directional. sdo ? serial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the AD9952 operates in a single bi-directional i/o mode, this pin does not output data and is set to a high impedance state. syncio ? synchronizes the i/o port state machines w ithout affecting the addressable registers contents. an active high input on the sync i/o pin causes the current communication cycle to abort. after sync i/o returns low (logic 0) another communication cycle may begin, starting with the instruction byte write. msb/lsb transqfers the AD9952 serial port can support both most signifi cant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the control register 00h<8> bit. the default value of control register 00h<8> is low (m sb first). when control register 00h<8> is set high, the AD9952 serial port is in lsb first form at. the instruction byte must be written in the format indicated by control register 00h<8>. that is, if the AD9952 is in lsb first mode, the instruction byte must be written from least significant bit to most significant bit. for msb first operation, the serial port controller will generate the most significant byte (of the specified register) address first followed by the ne xt lesser significant byte addresses until the io operation is complete. all data written to (read from) the AD9952 must be (will be) in msb first order. if the lsb mode is active, the serial port controller will generate the least significant byte address first followed by the next greater signi ficant byte addresses until the io operation is complete. all data written to (read from) the AD9952 must be (will be) in lsb first order. preliminary technical data AD9952 rev. pra 1/31/03 page 31 analog devices, inc. example operation to write the amplitude scale factor register in msb first format apply an instruction byte of 02h (serial address is 00010(b)). from this instruction, the internal controller w ill generate an internal byte address of 07h (see the register map) for the fi rst data byte written and an internal address of 08h for the next byte written. since the amplitude sc ale factor register is two bytes wide, this ends the communication cycle. to write the amplitude scale factor register in lsb first format apply an instruction byte of 40h. from this instruction, the intern al controller will generate an internal byte address of 07h (see the register map) for the first data byte written and an internal address of 08h for the next byte written. since the amplitude scale factor register is tw o bytes wide, this ends the communication cycle. notes on serial port operation 1) the AD9952 serial port configuration bits resi de in bits 8 and 9 of cfr1 (address 00h). the configuration changes immediately upon writing to this register. for multi-byte transfers, writing to this register may occur during the mi ddle of a communication cycle. care must be taken to compensate for this new configuration for the remainder of the current communication cycle. 2) the system must maintain synchronization with the AD9952 or the internal control logic will not be able to recognize further instruc tions. for example, if the system sends an instruction byte that describes writing a 2-byte register, then pulses the sclk pin for a 3- byte write (24 additional sclk rising edges), co mmunication synchronization is lost. in this case, the first 16 sclk rising edges after the instruction cycle will properly write the first two data bytes into the AD9952, but the next ei ght rising sclk edges are interpreted as the next instruction byte, not the final byte of the previous communication cycle. in the case where synchronization is lost between the system and the AD9952, the sync i/o pin provides a means to re-establish synchronization without re-initializing the entire chip. the sync i/o pin enables the user to reset the AD9952 state machine to accept the next eight sclk rising edges to be coincident with the instruction phase of a new communication cycle. by applying and removing a ?high? signal to the sync i/o pin, the AD9952 is set to once again begin performing the communication cycle in synchronization with the system. any information that had been written to the AD9952 registers during a valid communication cycle prior to loss of synchronization will remain intact. power down functions of the AD9952 the AD9952 supports an externally controlled, or hardware, power down feature as well as the more common software programmable power down bits found in previous adi dds products. the software control power down allows the dac , comparator, pll, input clock circuitry and the digital logic to be individually power down via unique control bits (cfr1<7:4>). with the exception of cfr1<6>, these bits are not active when the externally controlled power down pin (pwrdwnctl) is high. external power down control is supported on the AD9952 via the pwrdwnctl input pin. when the pwrdwnctl input pin is high, the AD9952 will enter a power preliminary technical data AD9952 rev. pra 1/31/03 page 32 analog devices, inc. down mode based on the cfr1<3> bit. when the pw rdwnctl input pin is low, the external power down control is inactive. when the cfr1<3> bit is zero, and the pwrdwnctl input pin is high, the AD9952 is put into a ?fast recovery power down? mode. in this mode , the digital logic and the dac digital logic are powered down. the dac bias circuitry, comparato r, pll, oscillator, and clock input circuitry is not powered down. the comparator can be powered down by setting the comparator power down bit, cfr1<6> =1. when the cfr1<3> bit is high, and the pwrdwnc tl input pin is high, the AD9952 is put into the ?full power down? mode. in this mode, all func tions are powered down. this includes the dac and pll, which take a significant amount of time to power up. when the pwrdwnctl input pin is high, the i ndividual power down bits (cfr1<7>, <5:4>) are invalid (don?t care) and are unused; however the comparator power down bit, cfr1<6>, will continue to control the power-down of the compar ator. when the pwrdwnctl input pin is low, the individual power down bits control th e power down modes of operation. note ? the power down signals are all designed such that a logic 1 indicates the low power mode and a logic zero indicates the active, or powered up mode. the table below indicates the logic level for e ach power down bit that drives out of the AD9952 core logic to the analog section and the digital cloc k generation section of the chip for the external power down operation. control mode active description pwrdwnctl = 0 cfr1<3> don?t care software control digital power down = cfr1<7> comparator power down = cfr1<6> dac power down = cfr1<5> input clock power down = cfr1<4> pwrdwnctl = 1 cfr1<3> = 0 external control, fast recovery power down mode digital power down = 1?b1; comparator power down = 1?b0 or cfr1<6>; dac power down = 1?b0; input clock power down = 1?b0; pwrdwnctl = 1 cfr1<3> = 1 external control, full power down mode digital power down = 1?b1; comparator power down = 1?b1; dac power down = 1?b1; input clock power down = 1?b1; table 7 power down control functions preliminary technical data AD9952 rev. pra 1/31/03 page 33 a n alog d e vices , inc. AD9952 application suggestions a d 9952 lpf refclk rf /if i nput m odulated/ demodulat ed s i gnal figure f s y nthesized l.o fo r u p conversion/ d o w n c onversion a d 9952 filter phase comparator loop filter vco tuning wo r d figure g digit a lly program mable ?divi d e-by-n? function in pll re f s i gnal AD9952 dds ad 9952 o n - ch ip co mparat or lp f lp f iou t tun i ng word iou t figure h frequenc y agile c l ock generator cmos level clock preliminary technical data AD9952 rev. pra 1/31/03 page 34 a n alog d e vices , inc. AD9952 d d s lpf iout freque ncy t u ning word crysta l out sy nc out pha s e offset word 1 sa w crystal AD9952 dds lpf iout freque ncy t u ning word sync in pha s e offse t wo rd 2 re f c l k re f c l k refcl k i baseba nd q b a se band rf out figure i tw o a d 9952s sync hronized to provide i & q c a rriers w i th independent phas e of fset s f o r n u lling |
Price & Availability of AD9952
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |